Semiconductor elements (power devices) which have a high breakdown voltage and allow a large current to flow therethrough are used in various fields. Conventionally, Si power devices in which silicon (Si) semiconductor is used have been in the mainstream. However, Si power devices have limited use due to the physical properties of Si semiconductor. In recent years, SiC power devices in which silicon carbide (SiC) semiconductor is used, which is a semiconductor material having a larger band gap (wide-band gap) than that of Si semiconductor, are being developed.
SiC semiconductor has higher breakdown voltage characteristics than those of Si semiconductor. Therefore, in a vertical power MOSFET in which SiC semiconductor is used, the drift region can be made thin, and also the impurity density in the drift region can be increased, thus making it possible to greatly reduce the drift resistance. Moreover, since SiC semiconductor has excellent heat conduction characteristics and high-temperature durability, the current-carrying capacity of an SiC power MOSFET can be easily improved.
However, while the drift resistance can be greatly reduced, an SiC power MOSFET has a problem of large channel resistance, which prevents its ON resistance from being sufficiently reduced. The reason why an SiC power MOSFET has a large channel resistance is described below.
In an SiC power MOSFET, generally speaking, a gate insulating layer (SiO2) is formed by performing a thermal oxidation treatment for the surface of an SiC layer. At the interface of the SiO2 layer thus formed and the SiC layer, interface states that trap a large number of carriers are formed with a high density. Therefore, when a channel is formed in these interfaces, the high-density interface states will decrease the carrier mobility (channel mobility) at the channel, thus increasing the channel resistance.
In order to reduce the channel resistance of a MOSFET, it is necessary to reduce the gate length (channel length) and reduce the cell pitch to enhance the degree of integration of unit cells.
Patent Document 1 discloses a method of utilizing a self-aligning process to form a source region within a well region, with a view to improving the channel resistance. According to this method, the gate length can be reduced, so that losses due to channel resistance can be suppressed.
FIGS. 10(a) to (c) are step-by-step cross-sectional views for describing a method of forming a source region according to a self-aligning process which is disclosed in Patent Document 1. Note that an MOSFET is typically constructed from a large number of unit cells which are arranged on a substrate, each unit cell being defined by a well region. FIGS. 10(a) to (c) only show portions of adjoining unit cells, among such unit cells.
First, as shown in FIG. 10(a), on an SiC layer 2 which is grown on a substrate (not shown), an SiO2 layer 24 is formed. Thereafter, by using this as a mask, impurity ions (conductivity type: e.g. p type) are implanted into the SiC layer 2. As a result, a plurality of well regions 6 are formed in the SiC layer 2, and the regions of the SiC layer 2 where the well regions 6 have not been formed become a drift region 2a. 
Then, as shown in FIG. 10(b), sidewalls (sidewall spacers) 25, which are in contact with the lateral walls of the SiO2 layer 24, and a resist layer 23 covering portions of the well regions 6 are formed. Specifically, an SiO2 film (not shown) is deposited on the substrate surface on which the SiO2 layer 24 is formed; by etching this back, the sidewalls 25 are obtained in a self-aligning manner. Next, a resist film (not shown) is deposited on the substrate surface, and thereafter is patterned through exposure and development, whereby the resist layer 23 is formed. As shown by dotted lines, in a portion 7′ of each well region 6 that is covered with the resist layer 23, a well contact region is formed in a subsequent step, which is a high-concentration p type region.
Next, as shown in FIG. 10(c), by using the SiO2 layer 24, the sidewalls 25, and the resist layer 23 as a mask, impurity ions (conductivity type: e.g. n type) are implanted into the SiC layer 2, thus obtaining source regions 8. The distance Lg between the end of a well region 6 and the end of a source region 8 on the surface of the SiC layer 2 defines the “gate length” of the MOSFET. The gate length Lg is determined by the width of the sidewalls 25. The width of the sidewalls 25 is controlled by the thickness of the SiO2 layer 24 for forming the sidewalls 25. Moreover, since the sidewalls 25 are formed through a self-aligning process which does not require mask alignment, variations in the gate length Lg due to misalignment of the mask are prevented, unlike in earlier processes. Therefore, as compared to earlier processes, the gate length Lg can be made substantially uniform.
Note that, at this step, impurity ions are not implanted into the portions 7′ to become the well contact regions, because they are covered with the resist layer 23. After the implantation, the SiO2 layer 24, the sidewalls 25, and the resist layer 23 having been used as a mask are removed.
Thereafter, by implanting impurity ions (conductivity type: e.g. p type) at a high concentration into the portion 7′ of each well region 6 that has been covered with the resist layer 23, a well contact region is obtained. Since n type impurity ions are not implanted into the portion 7′ to become the well contact region in the aforementioned step of forming the source regions 8, but only p type impurity ions are implanted in this step at a high concentration, a higher-concentration p type well contact region can be formed.
The well contact regions are provided for the following reasons. Generally speaking, in a power MOSFET, a source electrode to be formed on the SiC layer 2 needs to not only form an ohmic contact with a source region 8, but also form an ohmic contact with a well region 6 in order to fix the potential of the well region 6 to a reference potential. However, a semiconductor having a large band gap such as SiC is not likely to form a good ohmic contact. In order for a good ohmic contact to be formed, it is preferable to increase the impurity concentration in a portion of the surface of the well region 6 that joins the source electrode. Thus, a construction is employed where a high-concentration p type region (well contact region) is provided in the well region 6 to form a good ohmic contact between the well contact region and the source electrode.
According to the method described above with reference to FIG. 10, the sidewalls 25 are formed through a self-aligning process, which ensures that the gate length Lg is substantially uniform and short. Therefore, while minimizing deteriorations in the device characteristics due to variations in the gate length Lg (short channel effect), the channel resistance can be reduced.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2002-299620